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(c) 2014 . renesas electronics corporation. all rights reserved. page 1 of 1 date: jan . 30 , 201 4 renesas technical update 1753, shimonumabe, nakahara - ku, kawasaki - shi, kanagawa 211 - 8668 japan renesas electronics corporation product category mpu/mcu document no. tn -rx *-a086 a/e r ev. title information category applicable product rx63t group lot no. reference document rx63t group users manual: hardware rev.2.1 0 (r 01uh0238jj0210) all lots this document describes the corrections in rx 63t gro up users manual: hardware rev. 2.1 0. changes are underlined in the list below. page 52 correct a note to table 1.1 outline of specifications (7/7) . note 1. please contact renesas electronics sales office for derating of operation under ta = +85c to +105c. derating is the systematic reduction of load for the sake of improved reliability. 1 .00 technical notification rx 63t gro up users manual: hardware rev. 2.1 0 corrections of
renesas technica l update tn -rx *- a086a/e date: jan . 30 , 201 4 page 2 of 16 page 5 6 correct a description in table 1.3 list of products (5/5) . origin al t able on - chip rom on - chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature rx63t r5f563tbbdfp r5f563tbbdfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v - 40 to +85c (d version) r5f563tbbdfp r5f563tbbdfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563teedfb r5f563teedfb#v0 plqp0144ka - a 512 kbytes 48 kbytes can module not included r5f563teedfa r5f563teedfa#v0 plqp0120ka - a 512 kbytes 48 kbytes can module not included r5f563teedfh r5f563teedfh#v0 plqp0112ja - a 512 kbytes 48 kbytes can module not included r5f563teedfp r5f563teedfp#v0 plqp0100kb - a 512 kbytes 48 kbytes can module not included r5f563tcedfb r5f563tcedfb#v0 plqp0144ka - a 384 kbytes 32 kbytes can module not included r5f563tcedfa r5f563tcedfa#v0 plqp0120ka - a 384 kbytes 32 kbytes can module not included r5f563tcedfh r5f563tcedfh#v0 plqp0112ja - a 384 kbytes 32 kbytes can module not included r5f563tcedfp r5f563tcedfp#v0 plqp0100kb - a 384 kbytes 32 kbytes can module not included r5f563tbedfb r5f563tbedfb#v0 plqp0144ka - a 256 kbytes 24 kbytes can module not included r5f563tbedfa r5f563tbedfa#v0 plqp0120ka - a 256 kbytes 24 kbytes can module not included r5f563tbedfh r5f563tbedfh#v0 plqp0112ja - a 256 kbytes 24 kbytes can module not included r5f563tbedfp r5f563tbedfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module not included R5F563T6EDFM R5F563T6EDFM#v0 plqp0064kb - a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5edfm r5f563t5edfm#v0 plqp0064kb - a 48 kbytes 8 kbytes can module not included r5f563t4edfm r5f563t4edfm#v0 plqp0064kb - a 32 kbytes 8 kbytes can module not included r5f563t6edfl r5f563t6edfl#v0 plqp0048kb - a 64 kbytes 8 kbytes can module not included r5f563t5edfl r5f563t5edfl#v0 plqp0048kb - a 48 kbytes 8 kbytes can module not included r5f563t4edfl r5f563t4edfl#v0 plqp0048kb - a 32 kbytes 8 kbytes can module not included r5f563teagfb r5f563teagfb#v0 plqp0144ka - a 512 kbytes 48 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563teagfb r5f563teagfb#v1 plqp0144ka - a 512 kbytes 48 kbytes can module included r5f563teagfa r5f563teagfa#v0 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563teagfa r5f563teagfa#v1 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563teagfh r5f563teagfh#v0 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563teagfh r5f563teagfh#v1 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563teagfp r5f563teagfp#v0 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563teagfp r5f563teagfp#v1 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563tcagfb r5f563tcagfb#v0 plqp0144ka - a 384 kbytes 32 kbytes can module included r5f563tcagfb r5f563tcagfb#v1 plqp0144ka - a 384 kbytes 32 kbytes can module included
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 3 of 16 it should be: rx63t r5f563tbbdfp r5f563tbbdfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v - 40 to +85c (d version) r5f563tbbdfp r5f563tbbdfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563teedfb r5f563teedfb#v0 plqp0144ka - a 512 kbytes 48 kbytes can module not included r5f563teedfa r5f563teedfa#v0 plqp0120ka - a 512 kbytes 48 kbytes can module not included r5f563teedfh r5f563teedfh#v0 plqp0112ja - a 512 kbytes 48 kbytes can module not included r5f563teedfp r5f563teedfp#v0 plqp0100kb - a 512 kbytes 48 kbytes can module not included r5f563tcedfb r5f563tcedfb#v0 plqp0144ka - a 384 kbytes 32 kbytes can module not included r5f563tcedfa r5f563tcedfa#v0 plqp0120ka - a 384 kbytes 32 kbytes can module not included r5f563tcedfh r5f563tcedfh#v0 plqp0112ja - a 384 kbytes 32 kbytes can module not included r5f563tcedfp r5f563tcedfp#v0 plqp0100kb - a 384 kbytes 32 kbytes can module not included r5f563tbedfb r5f563tbedfb#v0 plqp0144ka - a 256 kbytes 24 kbytes can module not included r5f563tbedfa r5f563tbedfa#v0 plqp0120ka - a 256 kbytes 24 kbytes can module not included r5f563tbedfh r5f563tbedfh#v0 plqp0112ja - a 256 kbytes 24 kbytes can module not included r5f563tbedfp r5f563tbedfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module not included R5F563T6EDFM R5F563T6EDFM#v0 plqp0064kb - a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5edfm r5f563t5edfm#v0 plqp0064kb - a 48 kbytes 8 kbytes can module not included r5f563t4edfm r5f563t4edfm#v0 plqp0064kb - a 32 kbytes 8 kbytes can module not included r5f563t6edfl r5f563t6edfl#v0 plqp0048kb - a 64 kbytes 8 kbytes can module not included r5f563t5edfl r5f563t5edfl#v0 plqp0048kb - a 48 kbytes 8 kbytes can module not included r5f563t4edfl r5f563t4edfl#v0 plqp0048kb - a 32 kbytes 8 kbytes can module not included r5f563teagfb r5f563teagfb#v1 plqp0144ka - a 512 kbytes 48 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563teagfa r5f563teagfa#v1 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563teagfh r5f563teagfh#v1 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563teagfp r5f563teagfp#v1 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563tcagfb r5f563tcagfb#v1 plqp0144ka - a 384 kbytes 32 kbytes can module included on- chip rom on- chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 4 of 16 page 5 7 correct a description in table 1.3 list of products ( 4 /5) . origin al t able on - chip rom on - chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature rx63t r5f563tcagfa r5f563tcagfa#v0 plqp0120ka - a 384 kbytes 32 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563tcagfa r5f563tcagfa#v1 plqp0120ka - a 384 kbytes 32 kbytes can module included r5f563tcagfh r5f563tcagfh#v0 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcagfh r5f563tcagfh#v1 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcagfp r5f563tcagfp#v0 plqp0100kb - a 384 kbytes 32 kbytes can module included r5f563tcagfp r5f563tcagfp#v1 plqp0100kb - a 384 kbytes 32 kbytes can module included r5f563tbagfb r5f563tbagfb#v0 plqp0144ka - a 256 kbytes 24 kbytes can module included r5f563tbagfb r5f563tbagfb#v1 plqp0144ka - a 256 kbytes 24 kbytes can module included r5f563tbagfa r5f563tbagfa#v0 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbagfa r5f563tbagfa#v1 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbagfh r5f563tbagfh#v0 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbagfh r5f563tbagfh#v1 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbagfp r5f563tbagfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563tbagfp r5f563tbagfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563tebgfb r5f563tebgfb#v0 plqp0144ka - a 512 kbytes 48 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v r5f563tebgfb r5f563tebgfb#v1 plqp0144ka - a 512 kbytes 48 kbytes can module included r5f563tebgfa r5f563tebgfa#v0 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563tebgfa r5f563tebgfa#v1 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563tebgfh r5f563tebgfh#v0 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563tebgfh r5f563tebgfh#v1 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563tebgfp r5f563tebgfp#v0 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563tebgfp r5f563tebgfp#v1 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563tcbgfb r5f563tcbgfb#v0 plqp0144ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfb r5f563tcbgfb#v1 plqp0144ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfa r5f563tcbgfa#v0 plqp0120ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfa r5f563tcbgfa#v1 plqp0120ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfh r5f563tcbgfh#v0 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcbgfh r5f563tcbgfh#v1 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcbgfp r5f563tcbgfp#v0 plqp0100kb - a 384 kbytes 32 kbytes can module included r5f563tcbgfp r5f563tcbgfp#v1 plqp0100kb - a 384 kbytes 32 kbytes can module included
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 5 of 16 it should be: on- chip rom on- chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature rx63t r5f563tcagfa r5f563tcagfa#v1 plqp0120ka - a 384 kbytes 32 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563tcagfh r5f563tcagfh#v1 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcagfp r5f563tcagfp#v1 plqp0100kb - a 384 kbytes 32 kbytes can module included r5f563tbagfb r5f563tbagfb#v1 plqp0144ka - a 256 kbytes 24 kbytes can module included r5f563tbagfa r5f563tbagfa#v1 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbagfh r5f563tbagfh#v1 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbagfp r5f563tbagfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563tebgfb r5f563tebgfb#v1 plqp0144ka - a 512 kbytes 48 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v r5f563tebgfa r5f563tebgfa#v1 plqp0120ka - a 512 kbytes 48 kbytes can module included r5f563tebgfh r5f563tebgfh#v1 plqp0112ja - a 512 kbytes 48 kbytes can module included r5f563tebgfp r5f563tebgfp#v1 plqp0100kb - a 512 kbytes 48 kbytes can module included r5f563tcbgfb r5f563tcbgfb#v1 plqp0144ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfa r5f563tcbgfa#v1 plqp0120ka - a 384 kbytes 32 kbytes can module included r5f563tcbgfh r5f563tcbgfh#v1 plqp0112ja - a 384 kbytes 32 kbytes can module included r5f563tcbgfp r5f563tcbgfp#v1 plqp0100kb - a 384 kbytes 32 kbytes can module included
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 6 of 16 page 58 correct a description in table 1.3 list of products (5/5) . origin al t able on - chip rom on - chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature rx63t r5f563tbbgfb r5f563tbbgfb#v0 plqp0144ka - a 256 kbytes 24 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563tbbgfb r5f563tbbgfb#v1 plqp0144ka - a 256 kbytes 24 kbytes can module included r5f563tbbgfa r5f563tbbgfa#v0 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbbgfa r5f563tbbgfa#v1 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbbgfh r5f563tbbgfh#v0 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbbgfh r5f563tbbgfh#v1 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbbgfp r5f563tbbgfp#v0 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563tbbgfp r5f563tbbgfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563t6egfm r5f563t6egfm#v0 plqp0064kb - a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5egfm r5f563t5egfm#v0 plqp0064kb - a 48 kbytes 8 kbytes can module not included r5f563t4egfm r5f563t4egfm#v0 plqp0064kb - a 32 kbytes 8 kbytes can module not included r5f563t6egfl r5f563t6egfl#v0 plqp0048kb - a 64 kbytes 8 kbytes can module not included r5f563t5egfl r5f563t5egfl#v0 plqp0048kb - a 48 kbytes 8 kbytes can module not included r5f563t4egfl r5f563t4egfl#v0 plqp0048kb - a 32 kbytes 8 kbytes can module not included note 1. please contact us if you are using a g version.
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 7 of 16 it should be: on- chip rom on- chip ram operating operating group part no. order part no. package capacity capacity option voltage temperature rx63t r5f563tbbgfb r5f563tbbgfb#v1 plqp0144ka - a 256 kbytes 24 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v - 40 to +105c (g version)* 1 r5f563tbbgfa r5f563tbbgfa#v1 plqp0120ka - a 256 kbytes 24 kbytes can module included r5f563tbbgfh r5f563tbbgfh#v1 plqp0112ja - a 256 kbytes 24 kbytes can module included r5f563tbbgfp r5f563tbbgfp#v1 plqp0100kb - a 256 kbytes 24 kbytes can module included r5f563t6egfm r5f563t6egfm#v0 plqp0064kb - a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5egfm r5f563t5egfm#v0 plqp0064kb - a 48 kbytes 8 kbytes can module not included r5f563t4egfm r5f563t4egfm#v0 plqp0064kb - a 32 kbytes 8 kbytes can module not included r5f563t6egfl r5f563t6egfl#v0 plqp0048kb - a 64 kbytes 8 kbytes can module not included r5f563t5egfl r5f563t5egfl#v0 plqp0048kb - a 48 kbytes 8 kbytes can module not included r5f563t4egfl r5f563t4egfl#v0 plqp0048kb - a 32 kbytes 8 kbytes can module not included note: orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. note: the products with the product id code 1 (ex. r5f563teadfb#v1 ) are the revised version to the specification constraints of technical update tx - rx* - a84a / e described. note 1 . please contact renesas electronics sales office for derating of operation under ta = +85c to +105c. derating is the systematic reduction of load for the sake of improved reliability.
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 8 of 16 page 155 add the adgspmr register to table 6.1 list of i/o registers (address order) (20/56) . address module symbol register name register symbol number of bits access size number of access states module name reference page remarks iclk > pclk iclk < pclk 000890fch s12ad a/ d group scan prior it y con t rol register adgspmr 16 16 2 , 3 pclkb 2iclk s12adb not present in versions with 64 or 48 pins.
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 9 of 16 page 189 correct a description in table 6.1 list of i/o registers (address order) ( 54 /56) . iclk > pclk iclk < pclk 000c3002h dpc software start setting reg ister 0 softstar t0 16 16 3 to 5 pclka 2, 3 iclk 1633 not present in versions with 64 or 48 pins. 000c3006h dpc software start setting reg ister 1 softstar t1 16 16 3 to 5 pclka 2, 3 iclk 1633 not present in versions with 64 or 48 pins. 000c300ah dpc software start setting reg ister 2 softstar t2 16 16 3 to 5 pclka 2, 3 iclk 1633 not present in versions with 64 or 48 pins. 000c300eh dpc software start setting reg ister 3 softstar t3 16 16 3 to 5 pclka 2, 3 iclk 1633 not present in versions with 64 or 48 pins. 000c3012h dpc reference value setting reg ister 0 votarget 0 16 16 3 to 5 pclka 2, 3 iclk 1634 not present in versions with 64 or 48 pins. 000c3016h dpc reference value setting reg ister 1 votarget 1 16 16 3 to 5 pclka 2, 3 iclk 1634 not present in versions with 64 or 48 pins. 000c301ah dpc reference value setting reg ister 2 votarget 2 16 16 3 to 5 pclka 2, 3 iclk 1634 not present in versions with 64 or 48 pins. 000c301eh dpc reference value setting reg ister 3 votarget 3 16 16 3 to 5 pclka 2, 3 iclk 1634 not present in versions with 64 or 48 pins. 000c3022h dpc reference value select reg ister refsel 16 16 3 to 5 pclka 2, 3 iclk 1634 not present in versions with 64 or 48 pins. 000c3026h dpc pwm channel setting reg ister chlsel 16 16 3 to 5 pclka 2, 3 iclk 1635 not present in versions with 64 or 48 pins. 000c302ah dpc control enable setting reg ister enable 16 16 3 to 5 pclka 2, 3 iclk 1635 not present in versions with 64 or 48 pins. 000c302eh dpc control calculation parameter setting reg ister kp0 paramkp0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3032h dpc control calculation parameter setting reg ister ki0 paramki0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3036h dpc control calculation parameter setting reg ister kq0 paramkq0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c303ah dpc control calculation parameter setting reg ister kf0 paramkf0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c303eh dpc control calculation parameter setting reg ister kp1 paramkp1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3042h dpc control calculation parameter setting reg ister ki1 paramki1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3046h dpc control calculation parameter setting reg ister kq1 paramkq1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c304ah dpc control calculation parameter setting reg ister kf1 paramkf1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c304eh dpc control calculation parameter setting reg ister kp2 paramkp2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3052h dpc control calculation parameter setting reg ister ki2 paramki2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3056h dpc control calculation parameter setting reg ister kq2 paramkq2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c305ah dpc control calculation parameter setting reg ister kf2 paramkf2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. address module symbol register name register symbol number of bits access size number of access states module name reference page remarks dpc
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 10 of 16 page 190 correct a description in table 6.1 list of i/o registers (address order) ( 55 /56) . iclk > pclk iclk < pclk 000c305eh dpc control calculation parameter setting reg ister kp3 paramkp3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3062h dpc control calculation parameter setting reg ister ki3 paramki3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3066h dpc control calculation parameter setting reg ister kq3 paramkq3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c306ah dpc control calculation parameter setting reg ister kf3 paramkf3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c306ch dpc control calculation result hig her-order bits store reg ister 0 resultu0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c306eh dpc control calculation result lower-order bits store reg ister 0 resultl0 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3070h dpc control calculation result hig her-order bits store reg ister 1 resultu1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3072h dpc control calculation result lower-order bits store reg ister 1 resultl1 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3074h dpc control calculation result hig her-order bits store reg ister 2 resultu2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3076h dpc control calculation result lower-order bits store reg ister 2 resultl2 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c3078h dpc control calculation result hig her-order bits store reg ister 3 resultu3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c307ah dpc control calculation result lower-order bits store reg ister 3 resultl3 16 16 3 to 5 pclka 2, 3 iclk 1636 not present in versions with 64 or 48 pins. 000c307eh dpc input code monitor enable reg ister tmonen 16 16 3 to 5 pclka 2, 3 iclk 1637 not present in versions with 64 or 48 pins. 000c3082h dpc maximum input code monitor reg ister 0 tmonmax0 16 16 3 to 5 pclka 2, 3 iclk 1637 not present in versions with 64 or 48 pins. 000c3086h dpc minimum input code monitor reg ister 0 tmonmin0 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c308ah dpc maximum input code monitor reg ister 1 tmonmax1 16 16 3 to 5 pclka 2, 3 iclk 1637 not present in versions with 64 or 48 pins. 000c308eh dpc minimum input code monitor reg ister 1 tmonmin1 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c3092h dpc maximum input code monitor reg ister 2 tmonmax2 16 16 3 to 5 pclka 2, 3 iclk 1637 not present in versions with 64 or 48 pins. 000c3096h dpc minimum input code monitor reg ister 2 tmonmin2 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c309ah dpc maximum input code monitor reg ister 3 tmonmax3 16 16 3 to 5 pclka 2, 3 iclk 1637 not present in versions with 64 or 48 pins. 000c309eh dpc minimum input code monitor reg ister 3 tmonmin3 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c30a2h dpc overvoltag e output error judg ment threshold setting reg ister 0 errvth0 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c30a6h dpc overvoltag e output error judg ment threshold setting reg ister 1 errvth1 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c30aah dpc overvoltag e output error judg ment threshold setting reg ister 2 errvth2 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. dpc address module symbol register name register symbol number of bits access size number of access states module name reference page remarks
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 11 of 16 page 191 correct a description in table 6.1 list of i/o registers (address order) ( 56 /56) . iclk > pclk iclk < pclk 000c30aeh dpc overvoltag e output error judg ment threshold setting reg ister 3 errvth3 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. 000c30b2h dpc pwm shut-down at overvoltag e output error setting reg ister errdwn 16 16 3 to 5 pclka 2, 3 iclk 1638 not present in versions with 64 or 48 pins. dpc address module symbol register name register symbol remarks number of bits access size number of access states module name reference page page 525 correct a description in table 21.6 register settings for input/output pin function in 144- pin lqfp . psel[4:0]settings pin p10 p11 p12 p13 p14 0000 0b (initial value) hi - z 00010b mtclkd mtclkc 01010b cts2# rts2# ss2# sck2 10001b usb0_dprpd usb0_vbusen page 525 correct a description in table 21.9 register settings for input/output pin function in 64- pin lqfp . psel[3:0] s ettings pin p10 p11 0000b (initial value) hi - z 0010b mtclkd mtclkc
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 12 of 16 page 525 correct a description in 22.2.17 timer output master enable register (toer) . b it sy m b o l bit n ame des c r i p ti o n r /w b0 oe3b master enable mtioc3b 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b1 oe4a master enable mtioc4a 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b2 oe4b master enable mtioc4b 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b3 oe3d master enable mtioc3d 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b4 oe4c master enable mtioc4c 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b5 oe4d master enable mtioc4d 0: mtu3 output is disabled * 1 1: mtu3 output is enabled r/w b 7, b6 reserv ed t hese b i t s are al w ays re a d as 1 . the w ri t e value should be 1. r/w note 1. to output a non-active level from each pin when mtu output is disabled, make necessary settings for non-active level output from general i/o ports in the data direction registers (pdr) , port output data registers ( po dr), and port mode register (pmr) in advance. for details, refer to i/o ports section. page 883 correct a description in 24.2.26 general pwm timer cycle setting register (gtpr) . gtpr is a 16 - bit readable/writable register that sets the maximum count value of gtcnt. there is one gtpr counter for each channel. for saw waves, the value of ( gtpr + 1 ) is the cycle. for triangle waves, the value of (gtpr value 2) is the cycle. value written to gtpr is ignored when write - protection is set to the relevant channel by the gtwp.wpn bit (n = 0 to 7). page 911 correct a description in 24 .3.2.2 buffer operation for gtccra and gtccrb . (1) when gtccra or gtccrb functions as output compare register buffer transfer is performed at an overflow (during up - count operation) or an underflow (during down - count operation) in saw - wave mode, and at b oth crest and trough in triangle - wave mode.
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 13 of 16 add a chapter in 29.12 usage notes . 35.12.14 note in relation to transmit enable bit (te) when the scr.te bit is set to 0 (serial transmission disabled) with a pin functions as txdn (n = 0 to 3, 12), the pin output goes high impedance. to avoid the txdn line going high impedance, take any of the following methods. (1) connect pull - up resistor to the txdn line. (2) before setting the scr.te bit to 0, modify the pin function to "general i/o port, output", or, after setting the scr.te bit to 1, modify the pin function to txdn. page 1364 correct a description in table 31.8 operation in can reset mode and can halt mode . mode receiver transmitter transmitter can reset mode (forcible transition) canm[1:0] = 11b can module enters can reset mode without waiting for the end of message reception. can module enters can reset mode without waiting for the end of message transmission. can module enters can reset mode without waiting for the end of bus-off recovery. can reset mode canm[1:0] = 01b can module enters can reset mode without waiting for the end of message reception. can module enters can reset mode after waiting for the end of message transmission.*1,*4 can module enters can reset mode without waiting for the end of bus-off recovery. can halt mode can module enters can halt mode after waiting for the end of message reception.*2,*3 can module enters can halt mode after waiting for the end of message transmission.*1, *2, *4 [when the bom[1:0] bits are 00b] a halt request from a program will be accepted only after bus-off recovery. [when the bom[1:0] bits are 01b] can module automatically enters can halt mode without waiting for the end of bus-off recovery (regardless of a halt request from a program). [when the bom[1:0] bits are 10b] can module automatically enters can halt mode after waiting for the end of bus-off recovery (regardless of a halt request from a program). [when the bom[1:0] bits are 11b] can module enters can halt mode (without waiting for the end of busoff recovery) if a halt is requested by a program during bus-off. canm[1:0], bom[1:0]: bits in ctlr note 1. if several messages are requested to be transmitted, mode transition occurs after the completion of the first message transmission. in a case that the can reset mode is being requested during suspend transmission, mode transition occurs when the bus is idle, the next transmission ends, or the can module becomes a receiver. note 2. if the can bus is locked in dominant state , the program can detect this state by monitoring the eifr.blif flag. the can module does not enter can halt mode while the can bus is locked in dominant state. enter can reset mode instead. note 3. if a can bus error occurs during reception after can halt mode is requested, the can module enters can halt mode. however, the can module does not enter can halt mode when the can bus is locked in dominant state. note 4. if a can bus error or arbitration-lost occurs during transmission after can reset mode or can halt mode is requested, the can module enters the requested operating mode. however, the can module does not enter can halt mode when the can bus is locked in dominant state. page 1 251
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 14 of 16 page 1364 add a description in 34.2.12 a/d group scan priority control register (adgspcr) . pgs bit (group a priority control setting) this bit sets the priority of operation on group a. set this bit to 1 when giving priority to operation on group a . when the pgs bit is to be set to 1, the adcsr.adcs[1:0] bits must be set to 01b (group scan mode). if the bits are set to any other values, operation is not guaranteed. when the pgs bit has been set to 0, clear operation must be performed by software according to section 34.6.2, notes on stopping a/d conversion. when the pgs bit has been set to 1, make settings according to section 34.3.4.4,operation under group - a priority control. when operating under group - a priority control in the group - scan mode, set to 1 to the pgsc bit of the adgspmr register, or specify the frequency ratio between the peripheral module clock ( pclkb ) and a/d conversion clock, adclk (=pclkd ) as indicated below. a) pclkb = pclkd ( set the same value to the sckcr. pckb [3:0 ] and sckcr. pckd [3:0] ) b) pclkb/2 = pclkd (set a value which +1 is added to the one set to the sckcr. pckb [3:0] to the sckcr. pckd[3:0] ) page 1494 add a new register description in 34.2 register descriptions . 34.2.19 group scan priority control register (adgspmr) address s12ad: adgspmr 0008 90fch b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b7 b6 b5 b4 b3 b2 b1 b0 pgsc value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit symbol bit name description r/w b 1 4 - b 0 reserved these bits are read as 0. the write value should be 0. r/w b 1 5 pgsc clock frequency setting bit when operating under group- a priority control 0 : when operating under group - a priority control, frequency ratio between pclk and adclk is 2:1 or 1:1. 1: when operating under group-a priority control, frequency ratio between pcl k and adclk is 4:1 or over. r/w adgspmr should always be accessed in 1 6- bits.
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 15 of 16 page 1743 correct a descrip tion in table 42.1 absolute maximum ratings . item symbol value unit power supply voltage vcc, pllvcc C 0.3 to +6.5 v usb power supply voltage vcc_usb*1 C 0.3 to +6.5 v analog power supply voltage avcc0, avcc*2 C 0.3 to +6.5 v reference power supply vol tage vrefh0*2 C0.3 to avcc0 to + 0.3 v vref*2 C0.3 to avcc0 to + 0.3 v input voltage (except for ports 4 to 6, c, usb0_dp, and usb0_dm) v in C 0.3 to vcc + 0.3 v input voltage (usb0_dp and usb0_dm) v in C 0.3 to vcc_usb + 0.3 v input voltage (port 4) v in C0.3 to avcc0 to + 0.3 v i nput voltage (ports 5, 6, and c) v in C0.3 to avcc to + 0.3 v analog input voltage (port 4) v an C0.3 to avcc0 to + 0.3 v analog input voltage (ports 5, 6, and c) v an C0.3 to avcc to + 0.3 v operating temperature d version produ ct t opr C 40 to +85 g version product t opr C 40 to +105 c storage temperature t stg C 55 to +125 c page 1747 correct a description in table 42.6 permissible power consumption . table 42.6 permissible power consumption (g version product only) no te: common standard values for conditions not given in the table are listed as condition 1 to condition 3 below. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl 0 = 0v avcc0 = avcc = 4.0 to 5.5v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = - 40 to +105c. ta is common to conditions 1 to 3. item symbol typ. max. unit test conditions total permissible power consumption* 1 pd 325 mw 85c < ta 105c note. please contact renesas electronics sales office for derating of operation under ta = +85c to +105c. derating is the systematic reduction of load for the sake of improved reliability. note 1. the total power consumption of the whole chip including output current. c
renesas technica l update tn -rx*-a086a/e date: jan . 30 , 201 4 page 16 of 16 page 1767 correct a description in table 42.21 timing of the pwm delay generation circuit . condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = t opr . ta is common to conditions 1 to 3. page 1788 correct a description in table 43 .1 absolute maximum ratings . item symbol value unit power supply volt age vcc C 0.3 to +4.6 v i nput volt age ( except for por t s for 5 v tolera nt* 1 and port 4) vin C 0.3 to vcc + 0.3 v i nput vo lt age ( port 4) vin C0.3 to avcc0 to + 0.3 v i nput volt age ( por ts for 5 v tolera nt ) * 1 vin C 0.3 to +5.8 v analog power supply volt age avcc0*2 C 0 .3 to +4.6 v reference power supply voltage vrefh0*2 C0.3 to avcc0 to + 0.3 v analog input volt age ( port 4) v an C0.3 to avcc0 to + 0.3 v operating tem pera t ure d version product topr C 40 to +85 c g version product topr C 40 to +105 c sto rage te m peratu r e tstg C 55 to +125 c page 1791 correct a description in table 4 3.5 permissible power consumption . table 4 3.5 permissible power consumption (g version product only) condition: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v avcc0 = 3.0 to 3.6 v, v refh0 = 3.0 v to avcc0 t a = t opr item symbol typ. max. unit test conditions total permissible power consumption* 1 pd 150 mw 85c < ta 105c 64-pin version pd 120 mw 85c < ta 105 c 48-pin version note. please contact renesas electronics sales office for derating of operation under ta = +85c to +105c. derating is the systematic reduction of load for the sake of improved reliability. note 1. the total power consumption of the whole chip including output current.

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